The present invention relates generally to integrated circuit devices and fabrication methods therefor, and, more particularly, to transistors having a suppressed short channel effect and fabrication methods therefor.
With the recent trend toward finer semiconductor devices, the 2-dimensonal size of transistors has become generally smaller. Reduction in channel length and width of a transistor, however, may be problematic. Moreover, these problems may be more severe in nano-scale transistors.
If the channel length is reduced, the threshold voltage may be reduced, which may increase the response speed of the device. Unfortunately, punchthrough may occur, leakage current may increase due to the surface punchthrough and the lower threshold voltage, and a sub-threshold swing may deteriorate. That is, the short channel effect may degrade a switching characteristic of the transistor.
If the channel width is reduced, the driving current may decrease, which may reduce the operation speed of the transistor. Further, narrow-width effects may be intensified. Due to the above problems, it may be difficult to reduce the width of transistors so as to improve the operation speed of a device in a high performance SRAM. Moreover, it may be difficult to increase the integration density in such devices.